The HIGHER project is developing three Host Processor Modules (HPMs). Two of these integrate the Rhea2 processor and the third incorporates the EU Pilot RISC-V processor. EXTOLL contributed to the EU Pilot chip by providing Network on Chip (NOC-X) and Chip-to-Chip (EX_C2C) IPs. They serve to connect several RISC-V HPMs and form a crucial part of the compute clusters that will be enabled by the servers developed in the HIGHER project.
Current complex systems that consist of multiple specialized chips or chiplets require ultra-fast, highly scalable and reliable communication fabrics. The robust 2D mesh infrastructure of the NOC‐X IP provides such an interconnect. Its predictable routing, scalability and high bisection bandwidth minimize latency variability while performance and bandwidth increase with the number of chips, preventing the bottlenecks typical of ring or bus-based architectures.
The NOC-X features an injection bandwidth of 96GB/s at 1.5GHz per device port and a hop latency of one clock cycle on the EU Pilot chip. The 2D mesh topology fits best for the floor plan requirements and the AMBA5 CHI compliant protocol for the device ports enables coherent communication with additional support for virtual channels.
Seamless integration with EXTOLL’s Chip To Chip IP allows the NOC‐X to reach its full potential. EX_C2C utilizes EXTOLL’s High-Speed SerDes (Serializer/Deserializer) IP. With minimized protocol conversion and an optimized low-latency architecture, the SerDes maintains the characteristics of the NOC-X while providing high-speed serialized links for connecting to chips that are physically distant. The NOC-X intelligently maps the logical 2D mesh across physical die boundaries, treating EX_C2C links as native mesh connections rather than external ports, allowing for a truly unified communication model.
In the EU Pilot chip, the NOC-X serves as a connection network for its functional units. Its purpose is to connect the Atrevido RISC-V cores (A), the Home Nodes with their shared L2 caches, the LPDDR4 memory controllers and the PCIe controller (see Figure 1). Using EX_C2C links, the network can be extended to other chips.
Figure 1: EU Pilot Network on Chip Topology
The EX_C2C forwards the CHI channels onto a serialized interface using its own encapsulation protocol. It includes user-side buffering that is managed on both the user side and the serial side, using a credit based flow control scheme. Furthermore, the protocol ensures reliable transmission by the implementation of a cyclic redundancy check (CRC) based error detection and a retry mechanism. While traffic between channels is not ordered, traffic within each channel remains strongly ordered between transmission and reception on the user interfaces.
Additionally, NOC-X features native UCIe Interface Support, which allows the integration of various compute and memory chiplets from the rapidly expanding UCIe ecosystem.
Together, NOC-X and EX_C2C offer a complete chip/chiplet communication solution that transforms the complexity of multi-chip/chiplet integration into a streamlined, high-performance process. This intelligent 2D mesh is designed to meet the massive bandwidth, fine-grained coherence, and stringent latency requirements of next-generation compute platforms.