The HIGHER open-access initiative is now live. Partners, collaborators, and interested developers from the wider European community can request access to real RISC-V and Arm systems at the Barcelona Supercomputing Center (BSC) to port, build, run, and validate their HPC and cloud software stacks, well before HIGHER’s own processor modules reach integration.
Why now, and why it matters
HIGHER is building open, standards-based, rack-scale systems for next-generation cloud and edge services around European processor technology. Hardware and software need to mature in parallel, and waiting for the final silicon before touching the software would leave portability, packaging, and runtime problems to surface at the worst possible moment. The open-access platforms exist to move that work forward. They give real, Linux-capable, non-x86 targets on which teams can discover, early and cheaply, whether their code actually builds, boots, and behaves outside the mainstream x86 world.
Two families of platforms, two complementary roles
Access is offered on two tracks that deliberately cover different needs.
- The Arm track is provided through the NVIDIA Grace partition of MareNostrum 5 (NG-GRACE), a production EuroHPC system hosted at BSC. This is a large, high-core-count Arm environment, 144 Grace cores per node, high memory bandwidth, a modern InfiniBand interconnect, and the usual HPC toolchains and module system. It is the right place to check that build systems handle AArch64 cleanly, that dependencies are available, and to run reduced size workloads, microbenchmarks, and multi-threaded scaling tests on a real, operational Arm server at scale.
- The RISC-V track follows the Software Development Vehicle (SDV) methodology developed in earlier European processor initiatives. It combines several layers of fidelity: commercial off-the-shelf RISC-V boards assembled into small clusters (spanning different core counts and vector capabilities, from RVV 0.7.1 to the ratified Vector Extension 1.0), emulation environments based on QEMU with tracing and analysis tooling for architectural introspection, and a path toward FPGA and prototype hardware closer to the final target. This lets a component be compiled and functionally tested on a real board, inspected in an emulator to understand its instruction mix or vectorization behaviour, and later migrated toward project-specific hardware.
What you can do with it
The emphasis at this stage is functional and portability validation rather than headline performance numbers. On these platforms you can verify that software builds without hidden x86 assumptions, that third-party packages exist for the target, and that runtime scripts, container images, system calls, monitoring agents, and CI/CD flows behave correctly on non-x86 architectures. In practice, that is where cloud and edge stacks most often break, not in the compute kernel, but in packaging, dependency resolution, filesystem and page-size assumptions, or networking configuration. Catching those issues now, on real hardware, is a large part of the value.
These are early-evaluation environments, not the final HIGHER platform. They will not reproduce the exact target hardware or deliver definitive performance predictions. What they do give is a continuous, shared software-readiness process — build early, test often, remove architecture-specific assumptions, and arrive at the project hardware with a known-good software baseline already in hand.
Request access
If you are involved in HIGHER or working on software that will eventually need to run on European Arm or RISC-V systems you can request access now.
Request access: https://cloud.hca.bsc.es/nextcloud/index.php/apps/forms/s/X2PipJpfYwjxF94mC9SSFyjH
We look forward to seeing what the community builds on top of it.